In recent years, improvement the processing capability of a mobile phone is demanded as a result of improvement of communication quality and advanced multiple functions such as the execution environment of Web browser and Java (registered trademark), and installation of a CCD camera and a video telephone function. Accordingly, the mobile phone has been developed in which twin CPUs are mounted to have specialized purposes such as a CPU for a communication process relating to audio communication (i.e. baseband chip) and a CPU for application processes. The twin CPUs are regarded as an important technique particularly in third and following generations of mobile phones on which various high functional applications are installed and which require higher speed communication. In third-generation mobile phones which require multimedia functions as represented by a video telephone function, a large burden will be generated if a baseband chip executes a video image process. In such a case, it is desirable to mount a CPU exclusively used for an application from viewpoint of flexibility.
In a currently developed mobile terminal with twin CPUs mounted, a process to be executed by each of the CPUs is different depending on the terminal. For example, there is a mobile phone with twin CPUs mounted, in which an application one of the CPUs is used to carry out an operation which requires high-speed processes such as a video image process and a Java (registered trademark) process while basic software is operated on a baseband chip side in the same manner as conventional techniques. However, in this case, problems arise such that specification changes of applications and a communication system affect other software and an application portion cannot be formed before completion of the communication system.
Moreover, in the mobile phone industry under fierce development competition, it is a large burden for manufacturers to develop twin CPUs for every new model. In order to solve such problems, the mobile phones with twin CPUs mounted which are highly independent from each other have been developed in recent years, in which the baseband chip side is used exclusively for communication processes and an application CPU is used to execute other application functions (such as a telephone book function, Java (registered trademark) function, video image reproduction function, and a voice process function). By completely dividing the system into a communication system and an application system, parallel development of the application CPU and the communication CPU becomes possible, to improve development efficiency. As a result, manufacturers can reduce development costs and a development period.
Meanwhile, function fulfillment and extension of waiting time are considered to be important in mobile communication terminals as represented by the current mobile phones. Accordingly, it has been started to employ an intermittent reception function in a wide range for the purpose of lowering power consumption at the waiting time. The intermittent reception is a technique to repeat a reception state (or a wakeup mode) and a low power state (or a sleep mode) for a predetermined period so as to receive a signal from other communication apparatus only in the wakeup mode and stop receiving the signal in the sleep mode. Following techniques are disclosed as related art relating to the intermittent reception.
Japanese Patent Application Publication (JP-P2002-368676A) describes an intermittent reception method for reducing consumed power by operating a system clock generating section at a time of a normal operation and stopping the system clock generating section in a sleep state.
Japanese Patent Application Publication (JP-P2003-196097A) describes a technique, in which table data saved in a backup memory when a power source of an intermittent operation is turned on is loaded into a table data storage section, thereby a period of time to read data from a boot ROM can be shortened by the intermittent operation.
Japanese Patent Application Publication (JP-P2004-134904A) describes a technique to reduce consumed power by setting a time period in a intermittent reception state to be doubled if there is no incoming call during a preset reception interval time or more and a reception level is not equal to or more than a preset specified value.
FIG. 9 is a block diagram showing a configuration of a mobile communication terminal 1100 (e.g. mobile phone) using twin CPUs in a related art. Referring to FIG. 9, a method to use a program for performing an intermittent receiving operation (to be referred to as a program for the intermittent operation hereinafter) in the mobile communication terminal 1100 will be described.
The related-art mobile communication terminal 1100 includes an application side chip for executing various application processes except for communication processes, and a communication side chip for executing communication processes. The application side chip is provided with an application CPU 1110, a memory interface (I/F) 1120, a ROM 1130, a RAM 1140, an ACPU interface (I/F) 1150. The communication side chip is also provided with a communication CPU 1200, an internal memory 1210, a memory interface (I/F) 1220, a RAM 1230, a CCPU interface (I/F) 1240, a control interface (I/F) 1260, and a LSI 1270.
The application CPU 1110 acquires and executes application programs stored in the ROM 1130 or the RAM 1140 by controlling the memory I/F 1120. At this time, a part of application programs stored in the ROM 1130 is temporarily stored in the RAM 1140 and the application programs to be used are acquired from the RAM 1140 so as to execute applications. The ACPU I/F 1150 is connected to the CCPU I/F 1240 on the communication side to exchange data between the application side chip and the communication side chip under control of the application CPU 1110 or control from the CCPU I/F 1240. For example, mail data produced by a mail producing process is transferred to the communication side chip via the ACPU I/F 1150 and transmitted to the outside in a communication process by the communication CPU 1200.
The communication CPU 1200 carries out the communication operation by controlling the LSI 1270 via the control I/F 1260. At this time, the communication CPU 1200 writes and reads data and programs into and from the internal memory 1210 or the RAM 1230 by using a control signal. The memory I/F 1220 writes and reads data and programs into and from the RAM 1230 in accordance with a control signal sent from the communication CPU 1200 or the CCPU I/F 1240. The CCPU I/F 1240 controls data exchanges between the communication side chip and the application side chip in accordance with a control signal sent from the communication CPU 1200. The control I/F 1260 controls the LSI 1270 in accordance with a control signal sent from the communication CPU 1200, and transfers various kinds of data from the LSI 1270 to the communication CPU 1200. The LSI 1270 is an integrated circuit which includes a base band unit, a wireless unit and a power circuit or the like to execute communication processes.
With the aforementioned configuration, communication programs and intermittent operation programs stored in the ROM 1130 and the RAM 1140 on the application side are transferred to the RAM 1230 on the communication side at the start time or when a normal operation mode and an intermittent receiving mode are switched in the mobile communication terminal 1100. The communication CPU 1200 executes communication processes and intermittent receiving operation processes by accessing the RAM 1230 which stores these programs.
The communication CPU 1200 in the related art controls the RAM 1230 to store the programs for the intermittent operation at a time of the intermittent receiving operation and accesses the RAM 1230 to execute the intermittent receiving operation (i.e. an operation to repeat the wakeup mode and the sleep mode). Therefore, an access to the RAM 1230 during the intermittent receiving operation requires extra power consumption.
Moreover, since the communication programs and the programs for the intermittent operation are both stored in the RAM 1230 during the intermittent receiving operation, it is necessary to ensure that the RAM 1230 has a capacity to store at least both programs. That is, an increase in the capacity of the RAM 1230 causes a circuit area and manufacturing costs to be increased.